High Performance 16-bit CPU with 4-Stage Pipeline
– 80/60/50 ns Instruction Cycle Time at 25/33/40 MHz CPU Clock
– 400/303/250 ns Multiplication (16 × 16 bit), 800/606/500 ns Division (32-/16-bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 MBytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
INFINEON IC Integrated Circuit SAK-C167CS-LM
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