Features • Integrated MAC and PHY Ethernet Controller Fully Compliant with IEEE 802.3/802.3u Standards • Designed for High Performance and High Throughput Applications • Supports 10BASE-T/100BASE-TX • Supports IEEE 802.3x Full-Duplex Flow Control and Half-Duplex Backpressure Collision Flow Control • Supports DMA-Slave Burst Data Read and Write Transfers • Supports IP Header (IPv4)/TCP/UDP/ICMP Checksum Generation and Checking • Supports IPv6 TCP/UDP/ICMP Checksum Generation and Checking • Automatic 32-Bit CRC Generation and Checking • Simple SRAM-like Host Interface Easily Connects to Most Common Embedded MCUS • Supports Multiple Data Frames for Receive without Address Bus and Byte-Enable Signals • Supports Both Big- and Little-Endian Processors • Larger Internal Memory with 12 kb for RX FIFO and 6 kb for TX FIFO. Programmable Low, High and Overrun Watermark for Flow Control in Rx FIFO • Shared Data Bus for Data, Address, and Byte Enable